1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof and, more particularly, to a multi-chip module having bonding wires and method of fabricating the same.
2. Description of the Related Art
As portable electronic devices become smaller, the dimensions of semiconductor packages in the electronic devices must also be reduced. To help accomplish this, a multi-chip module technique is widely used because it can increase the capacity of the semiconductor package. Multi-chip modules (MCMs) include a plurality of chips, which are stacked.
FIG. 1 is a cross sectional view illustrating a conventional multi-chip module having bonding wires.
Referring to FIG. 1, a bottom chip 3 and a top chip 7 are sequentially stacked on a substrate such as a lead frame or a printed circuit board. The substrate includes a flat body 1 and a first group of interconnections 1a and a second group of interconnections 1b formed on a surface of the body 1. The bottom chip 3 is attached and fixed to the body 1 using an adhesive 5, which is interposed between the bottom chip 3 and the body 1. Spacers 9 are interposed between the top chip 7 and the bottom chip 3 in order to separate the top chip 7 from the bottom chip 3. The bottom chip 3 has a plurality of pads 3a formed on its edges.
The pads 3a are electrically connected to the first group of interconnections 1a through a first group of bonding wires 13. In this case, the first group of bonding wires 13 may be in contact with a backside surface of the top chip 7 if the top chip 7 has the same dimension as the bottom chip 3. Thus, the spacers 9 should have a sufficient height to prevent the first group of bonding wires 13 from being in contact with the backside of the top chip 7. In other words, a distance S between the bottom chip 3 and the top chip 7 should be determined in consideration of the height of the first group of bonding wires 13. Accordingly, there is a limitation in reducing the total thickness of the multi-chip module.
Further, the top chip 7 has a plurality of pads 7a formed on its edges. The pads 7a are electrically connected to the second group of interconnections 1b through a second group of bonding wires 15. The space between the bottom chip 3 and the top chip 7 is filled with an insulator 11.
FIG. 2 is a cross sectional view illustrating another conventional multi-chip module having bonding wires.
Referring to FIG. 2, a bottom chip 23 and a top chip 27 are sequentially stacked on a substrate such as a lead frame or a printed circuit board. The substrate has the same configuration as the substrate described in FIG. 1. That is to say, the substrate includes a flat body 21 and a first group of interconnections 21a and a second group of interconnections 21b formed on a surface of the body 21. Also, the bottom chip 23 is attached and fixed to the body 21 using an adhesive 25, which is interposed between the bottom chip 23 and the body 21. An insulator 29 is interposed between the chips 23 and 27 in order to separate the top chip 27 from the bottom chip 23. The bottom chip 23 has a plurality of pads 23a formed on its edges.
The pads 23a are electrically connected to the first group of interconnections 21a through a first group of bonding wires 31. In this case, the first group of bonding wires 31 may be in contact with a backside surface of the top chip 27 if the top chip 27 has the same dimension as the bottom chip 23. Thus, the insulator 29 should have a sufficient thickness to prevent the first group of bonding wires 31 from being in contact with the backside of the top chip 27. In other words, a distance S between the bottom chip 23 and the top chip 27 should be determined in consideration of the height of the first group of bonding wires 31. Accordingly, there is a limitation in reducing the total thickness of the multi-chip module.
Further, the top chip 27 has a plurality of pads 27a formed on its edges. The pads 27a are electrically connected to the second group of interconnections 21b through a second group of bonding wires 33.
In the meantime, a multi-chip module is taught in U.S. Pat. No. 6,333,562 B1 to Lin, entitled “Multichip module having stacked chip arrangement”. In addition, U.S. Pat. No. 6,388,313 B1 discloses a multi-chip module having a bottom chip and a top chip, which are sequentially stacked.
According to the aforementioned conventional MCMs, it is difficult to prevent bonding wires connected to the bottom chip from contacting the backside surface of the top chip. Therefore, it is difficult to realize a thin and reliable package module.